As the semiconductor industry has progressed into nanometer technology process nodes in pursuit of higher device density and better performance, three-dimensional designs, such as fin field effect transistor (FinFET) devices, have been introduced into many logic and applications. One type of FinFET device is fabricated with multiple fin-like structures expanding vertically from a surface of a substrate. These fin-like structures are separated from each other by a shallow trench isolation (STI) region. Each of the fin-like structure has source/drain regions and a channel region formed between the source and drain regions. A metal gate is wrapped around the channel region of each fin-like structure, allowing better control of current flow from three sides of the channel region.
An issue associated with the above FinFET device is that the depth of trenches for forming source/drain contacts (electrically coupled to the source/drain regions for interlayer connection) at the STI region and the depth of trenches for forming source/drain contacts at the active region that includes the source/drain regions and the channel regions are different due to pattern-loading effects, which would occur when there is a difference in pattern densities between the STI region and the active region. Such a difference in depth may cause distortion of the trench profile after the trenches are filled with a conductive material. As a result, the performance of the device is degraded.